Complementary metal-oxide-semiconductor (CMOS) technology is used in microprocessors, static random access memories, and other types of digital logic integrated circuits and analog integrated circuits. Generally, CMOS technology relies on complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) to implement logic functions. Conventional planar device structures for a MOSFET include an active semiconductor layer, a source and a drain defined in the active semiconductor layer, a channel defined in the active semiconductor layer between the source and drain, and a gate electrode. The material constituting the gate electrode in such conventional planar device structures contains polycrystalline silicon (polysilicon) or a metal applied by an additive process that involves deposition of the material and patterning with a conventional lithography and etching process. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, an inversion or depletion layer is formed in the channel by the resultant electric field and carrier flow occurs in the depletion layer between the source and drain (i.e., the device output current).
Semiconductor-on-insulator (SOI) substrates may be advantageous for implementing MOSFETs in CMOS integrated circuits. In comparison with conventional bulk silicon MOSFETs, the use of an SOI substrate permits MOSFETs to operate at significantly higher speeds with improved electrical isolation and reduced electrical losses. High performance CMOS demands thin SOI layers, which permits the MOSFETs to operate in a fully-depleted state in which the depletion layer extends to the interface between the SOI layer and the buried oxide layer under typical control voltages.
In certain CMOS designs, low-voltage MOSFETs and high-voltage MOSFETs are integrated into a single integrated circuit. The former device type is used for logic functions. The latter device type is used for analog functions and for any special circuits requiring relatively high operating voltages and relatively low gate tunneling currents. This single chip implementation may be accomplished by reliance on thin gate oxide layers (e.g., 1 nm to 1.5 nm) for low-voltage MOSFETs and thick gate oxide layers (e.g., 2.5 nm to 4 nm) for high-voltage MOSFETs. Thick gate oxides may be difficult to perfect in high-performance CMOS because of the relatively small thickness of the SOI layer. Moreover, integration of both low-voltage and high-voltage MOSFET devices in a single integrated circuit in conventional CMOS fabrication schemes may require a relatively large number of fabrication steps and a large number of different masks for concurrent fabrication.
Consequently, improved device structures and fabrication methods are needed for high voltage MOSFETs that overcome these and other deficiencies of conventional device structures for high-voltage MOSFETs and conventional fabrication methods.